Conventional read/write memories, for example static random access memories (SRAMs), as are commonly used in computer systems often include redundant storage elements. These elements (arranged as redundant rows and/or columns which may be located adjacent to a regular memory core) may be utilized in the event some of the regular storage elements of a memory core are found to be defective. Thus, during write operations (e.g., where data is written to the memory device) there is a need to provide a redundant column with appropriate data signals.
In the past, two schemes (or variations thereof) have generally been available to write data to redundant columns of a memory device. A popular choice was to use transmissions gates to pass data from a selected pair of global data lines to a pair of redundant data lines. An implementation of such a scheme is shown in FIG. 1, where the redundant data write driver 10 shown in the dotted outline is repeated identically for each pair of internal data lines. Thus, for an embodiment with eight pairs of data lines, seven more identical redundant data write drivers, e.g., for a total of eight, are provided. The seven identical redundant data write drivers not shown in the figure are driven by the remaining seven pairs of global data lines (GDWx and GDWx, x=0-6) and seven select lines (QSELx, x=0-6).
For this and similar schemes, a pair of internal data write signals (DIN7 and DIN7) 12 and 14 are gated by an internal write signal (INTW) 16 in a write control driver 18 to produce a pair of global data write signals. For the illustrated case, assume that a column of a memory core which would ordinarily receive data signals GDW7 and GDW7 (from signals DIN7 and DIN7 gated by INTW) is replaced by a redundant column. Hence DIN7 and DIN7 are provided to the write control driver 18 along with the internal write signal (INTW) 16. The resulting global data write signals GDW7 20 and GDW7 22 are provided to the global data write bus 24 and to the redundant data write driver 10. Typically, DIN7 and DIN7 are always the logic complement of each other; however, GDW7 and GDW7 are logic high except during periods when the internal write pulse INTW is active, when they are true and complement of one another.
In order to transfer the logic states of the global data write signals GDW7 20 and GDW7 22 to the redundant data write lines RD and RD control logic 26 is used to enable the corresponding redundant data write driver 10. In particular, one of the eight select signals QSELx (x=0-7), in this case QSEL7, will be brought to a logic high to enable the corresponding redundant data write driver 10. The effect of this signal is to open transmission gates 28 and 30, allowing the pair of global data lines 20 and 22 to pass data to the redundant data write lines RD and RD. Because redundancy has been selected, signal RCEN (Redundant Column Enable) is active (logic high), thus disabling the static pull-up transistors 32 and 34. Thus, these transistors are prevented from helping in the recovery of the redundant data write lines after a write operation.
The above not only describes the operation of this prior scheme, but also highlights two of its disadvantages: (a) it inconsistently loads the global data write bus 24, loading heavier the pair of global data lines 20 and 22 which also drive the redundant data write lines RD and RD; and (b) it does not use the redundant data write line p-channel pull-up transistors 32 and 34 to help the recovery of the redundant data write lines, the recovery being left for the specific write control driver 18 associated with the pair of global data write lines 20 and 22, already heavier loaded than the rest of the global data write lines.
Another common solution is to use static pull-up transistors, such as transistors 46 and 48 shown in FIG. 2, to hold the redundant data lines (RD and/or RD) at a logic high potential in the absence of either a redundancy write operation or a logic low global data write signal. During a redundancy write operation, the redundant data write driver 40 pulls down one of the redundant data lines to a logic low potential when a logic low global data write signal is asserted. For this scheme (or variations thereof), eight parallel paths to ground (one for each data bit, x=0-7) are provided for each redundant data line, each with two n-channel transistors, e.g., 42 and 44, forming a wired-OR circuit. This wired-OR circuit is used to pull down the appropriate redundant data line (RD or RD) during a write operation to the redundant column. In this case, however, the write operation (i.e., to pull down the potential of the redundant data line to a logic low) "fights" against the action of the static p-channel pull-up transistors 46 and 48. Thus, the sizing of these pull-up transistors 46 and 48, which need to be small enough to limit the crowbar (a condition characterized by a direct path between a voltage source and ground and, hence, one in which a significant amount of current is consumed) on the redundant data write lines during a write, but also strong enough to ensure a fast recovery of the redundant data write lines at the end of write, becomes important. Hence, although simple, the static pull-up transistor implementation of FIG. 2 has the disadvantage of largely crowbarring the redundant data write lines (thus increasing the time required to complete the write operation) for sufficient redundant data write line recovery at the end of write.
Accordingly, what is desired is a scheme to drive redundant data write lines of a memory device which preferably loads consistently the data input lines independent of whether redundancy is used or not and which avoids the large crowbar conditions (while still retaining the short recovery times) present in the redundant data write line driving schemes of the past.